The present invention relates to semiconductor memory devices, and in particular to charge storage semiconductor memory devices of MNOS structure.
Because of its excellent memory operational characteristics, MNOS (metal-nitride-oxide-semiconductor) technology is experiencing increasing application to various types of semiconductor integrated circuit memory arrays, such as EAROM's, WAROM's, and NVRAM's. In order to minimize the complexity, power dissipation and cost of a chip which uses MNOS devices (indeed any type of semiconductor device), it is desirable to keep the operating voltages to a minimum number of preferably small magnitude voltages.
Consider as an example an MNOS NVRAM (NonVolatile Radom Access Memory). The volatile RAM part of such a device typically requires a 5 volt power supply and a ground connection. In addition, the nonvolatile memory portion requires a gate voltage of approximately 30 volts magnitude for writing, and a control voltage (applied to the channel via the source or drain) of about the same magnitude. Reduced complexity, power dissipation and cost could be achieved by decreasing the control voltage and the gate voltage requirements so that the RAM 5 volt power supply can be used to supply the control voltage and the gate voltage.
There are other, operational reasons for using low voltages. This is particularly true of n-channel MNOS integrated devices, which have unique problems at high voltages. For example, these devices exhibit relatively low breakdown voltages and are susceptible to avalanching and other voltage-related phenomena.
N-channel MNOS devices are also susceptible to channel dopant-sensitive spurious writing during channel-shielded operation. MNOS n-channel devices typically are adjusted to enhancement operation by implanting the substrate with p-type ions such as boron. A device, initially in a low threshold voltage, "0" state, will be channel-shielded and thereby prevented from writing to a "1" state when the gate is pulsed with a large positive voltage, +V, and the source is also pulsed with a positive voltage, with the substrate at ground. A channel is formed from the source to the drain, but the positive source voltage is applied to the channel, thereby diminishing the potential difference between the gate and the substrate and preventing writing. Consequently, the threshold remains at the low magnitude voltage. To write the device to a "1" state, the gate is again pulsed to +V with the substrate at 0 volts, but this time the source is at, e.g., 0 volts. Here, the channel potential is 0 volts and a high voltage field is present from the gate to the channel. As a result, negative charge tunnels from the substrate to the silicon dioxide-silicon nitride gate dielectric and is trapped therein, raising the threshold to, e.g., about +10 volts. When the channel-shielded MNOS device is sensitive to the enhancement impurity concentration, excessive impurity concentration can cause breakdown between the channel and the substrate during the channel-shielded operation. The channel-shielded operation may then cause unwanted avalanche writing of the device to the "1" state.
The MNOS microelectronics industry has addressed itself to decreasing high gate voltages with mixed success. For example, U.S. Pat. No. 4,019,198 issued Apr. 19, 1977 to Endo et al. relates to a nonvolatile p-channel MNOS semiconductor memory device having a high concentration impurity layer of the same conductivity type as the substrate surrounding the source and/or the drain. The aim of the patent is to use avalanche 0 writing (erasing) caused by the impurity layer to provide relatively low 0 write (erase) voltages and a large threshold window.
U.S. Pat. No. 4,017,888 issued Apr. 12, 1977 to Christie et al. relates to a nonvolatile depletion structure n-channel MNOS memory device which is written by pn junction avalanche breakdown. The device includes a substrate of a first conductivity type (p-), and a source and drain of the second conductivity type (n) which are connected by a permanent channel (n) to form a depletion mode structure. A highly doped layer of the first conductivity type (p+) underlies the permanent channel. This channel is separated from the gate electrode by a dual dielectric, including a relatively thick 75 Angstrom memory oxide.
The Christie device is written to a "1" state by applying a +18 volt signal through the gate with the source and drain at +10 volts and the substrate at ground. These voltages cause avalanche breakdown of the pn junction between the n-channel and the doped p-layer and thereby inject hot electrons into the dielectric to write the device to a reported threshold of approximately 10 volts. Applying +18 volts to the gate with the source, drain and substrate at ground erases the device.
Despite the improvements exemplified by the above patents, it is apparent there is a need for devices which use low write voltages.